In circuits, data signals must often be passed between components. Passing of signals between components must be done in a way that ensures that the circuit functions reliably for the voltages and speeds at which the circuit is expected to operate.
Such reliability is readily achieved for synchronous circuits that operate on the same clock speed and same voltage. Mobile devices and other devices where power saving is desired often have circuit portions that operate on different clock speeds and/or different voltages (or can switch between different clock speeds and voltages) to conserve power. Portions of the mobile devices do not have the same voltages and/or clock speeds. These different portions cannot be treated as synchronous circuits due to different voltage and/or clock speeds affecting the speed of the circuit and wires differently.
To accommodate this asynchronicity, asynchronous FIFO memory and a level shifter are inserted in the data path. Such FIFO memory and level shifter is shown in FIG. 1. As shown in FIG. 1, in order to adjust the signal provided to component 150 (shown as a flip-flop), data from the read pointer 152 in domain 2 (shown as Voltage B) is sent through level shifter 125 to multiplexer logic 120 where it is combined with the data values. The output of multiplexer logic 120 is then routed back through level shifter 125 before it is provided to component 150.
This operation (traversing through level shifter 125 twice and passing through read multiplexer logic 120) needs to be able to be completed within a single clock cycle to provide appropriate data fidelity. While this is no problem for low frequency implementations, if the clock is running at high frequency (e.g., 1 GHz and beyond), meeting single clock cycle timing is no longer possible.
Transfer of data across domains has been performed by requiring synchronicity between domains. However, as bus width increases, enforcing and achieving such synchronicity is more difficult and less reliable. Thus, such solutions are not readily scalable. Additionally, the likelihood of encountering bus skew (timing error) is exacerbated in high frequency systems.
Furthermore, as die size increases, the fluctuation on speed, voltage, and temperature have a greater effect on the overall performance of the circuit. Accordingly, variations in these factors have greater effects that can take circuits out of synchronicity. Thus, requiring circuit portions to be synchronous for domain transfers is more taxing on design tolerances and is less reliable.
Accordingly, there exists a need for an improved method and apparatus that provides for cross boundary (voltage and/or clock) data transmission that can reliably handle clock cycles of 1 GHz or greater.